1. Field of the Invention
The present invention relates to generally an interrupt information interface system and, more particularly, to an interface system in which a single interface information line is used between the external sources of interrupt or interrupt condition memories and a computer proper.
2. Description of the Prior Art
Referring to FIG. 1, a typical interrupt information interface system for use with a computer will be described. Reference numeral 4 designates a computer proper, and portion 1 corresponds to interrupt level memory registers positioned outside the computer. For each of n interrupt levels, one register is provided, and each level consists of m interrupts each of which corresponds to each bit of each register. Thus, nXm interrupt information lines are provided for setting interrupt information. When an interrupt condition occurs, the corresponding bit of the interrupt level memory register 1 is set to a logical "1". The logic sum of all of the interrupts in each of the registers is derived through an OR gate 3.
The outputs of the OR gates 3 are transmitted through interface lines 12 to an interrupt receiving register 5 in the computer proper 4. Each bit of the register 5 corresponds to each of the interrupt levels, respectively. When an interrupt is set to any bit of any interrupt level memory register 1, the corresponding bit of the interrupt receiving register 5 is set to a logical 1 through the OR gates 2 and the interface lines 12. An interrupt mask register 6 masks the reception of any desired interrupt level, and has a number of bits equal to the number of the interrupt levels, each bit corresponding to each bit of the register 5. The bits of the interrupt mask register 6 are set through set bus lines 10 in a hardware or software manner.
An AND gate 7 is provided to obtain the logic product of the corresponding bits of the registers 5 and 6. When an interrupt signal is set into the interrupt receiving register 5 and the corresponding bit of the interrupt mask register 6 is 1, that is, when the interrupt level is not masked, the output of the AND gate 7 is applied to a control gate 13 through an OR gate 8. Reference numeral 9 denotes an output line of an interrupt mask flip-flop (not shown) for masking temporarily all of the interrupts. That is, if the signal on the output line 9 is "0", no interrupt is permitted.
When the signal on the output line 9 is 1, the interrupt pulse is transmitted to and sets a receiving flip-flop 14 through the control gate 13 so that the signal is transmitted through an output line 14.sub.o for the processing of interrupt.
In the conventional interface system of the type described hereinbefore, interrupt signal lines 12 equal in number to the number n of interrupt levels are required. The number of interrupt levels varies dependent upon the use and type of an electronic computer, and is generally 8 - 32 and more than 128 when a computer is used for process control.
When the number of interrupt information lines is increased, wiring becomes very complex and expensive, but these problems are not so serious in case of the conventional computers.
LSI techniques have been recently so progressed that one computer is provided on only one chip. The above problems are very serious in case of the LSI computers. That is, the interface between the computer and peripheral equipment is restricted because of the limited number of terminals on the LSI chip so that it becomes extremely difficult to use the conventional interface system in the highly integrated LSI computers. Especially, in the case of a computer formed in one LSI chip to be referred to as a "one-chip computer" in this specification, the number of pins on a chip is limited, so that it is impossible to apply the conventional interface system. When the number of pins is increased, the yield is reduced, the reliability is adversely affected, and the cost becomes very expensive.